ERSA'11

The 2011 International Conference on Engineering of Reconfigurable Systems and Algorithms

ISBN #:  1-60132-177-5

EDITOR:
Toomas P. Plaks

ASSOCIATE EDITORS:
Shiu-Kai Chin, Pedro C. Diniz, William L. Harrison, Roman Lysecky

Foreword

SESSION: WORLDCOMP + ERSA KEYNOTE

How Engineering Mathematics can Improve Software

David Lorge Parnas

SESSION: ERSA/WORLDCOMP TUTORIAL

A Run-Time Evolvable Hardware Tutorial

Jim Torresen

SESSION: INVITED SESSION - CREATING THE SCIENCE + ENGINEERING FOR

CYBER-SECURITY

Logic Design for Access Control, Security, Trust and Assurance

Shiu-Kai Chin

Science of Mission Assurance

Sarah L. Muccio, Thomas N. J. Vestal

A Channel-theoretic Account of Separation Security

Gerard Allwein, William Harrison

It Takes a Village (to create a science): From Crypto Science to Security Science

Steven Borbash, Brad Martin, Robert Meushaw

SESSION: INVITED SESSION - RC + LBS: THE CONFLUENCE OF SECURE HARDWARE AND

PROGRAMMING LANGUAGES

3-D Extensions for Trustworthy Systems

Ted Huffmire, Timothy Levin, Cynthia Irvine, Ryan Kastner, Timothy Sherwood

Declarative FPGA Circuit Synthesis using Kansas Lava

Andy Gill

Towards Semantics-directed System Design and Synthesis

William Harrison, Benjamin Schulz, Adam Procter, Andrew Lukefahr, Gerard Allwein

SESSION: REGULAR SESSION - SECURITY: THREATS AND SOLUTIONS

Enforcing Information Flow Guarantees in Reconfigurable Systems with Mix-Trusted IP

Ryan Kastner, Jason Oberg, Wei Hu, Ali Irturk

Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques

Jurgen Teich, Daniel Ziener

Establishing Dedicated Functions on FPGA Devices for High-Performance Cryptography

Tim Guneysu

Elliptic Curve Cryptography on FPGAs: How Fast Can We Go with a Single Chip?

Kimmo Jarvinen

SESSION: REGULAR PAPERS

Hardware Architecture for Simultaneous Arithmetic Coding and Encryption

Amit Pande, Joseph Zambreno, Prasant Mohapatra

SESSION: REGULAR SESSION - RECONFIGURABLE AND EVOLVABLE HARDWARE

ARCHITECTURES

Heterogeneous Accelerated Bioinformatics – Perspectives for Cancer Research

Eric Stahlberg, Thomas Steinke, Melissa Smith, Sunita Chandrasekaran, Barbara Chapman

Reconfigurable and Evolvable Architectures and their Role in Designing Computational Systems

Andy Tyrrell

Next Generation Sequencing Data Processing. How reconfigurable computing can help?

Dominique Lavenier

Design-Space Exploration of Systolic Arrays for Biosequence Algorithms

Jeremy Buhler, Roger Chamberlain, Arpith Jacob

SESSION: INVITED SESSION - RUNTIME ADAPTIVE EMBEDDED SYSTEMS AND

ARCHITECTURES

i-Core: A Run-time Adaptive Processor for Embedded Multi-core Systems

Jorg Henkel, Lars Bauer, Michael Huebner, Artjom Grudnitsky

Advanced Profiling of Applications for Heterogeneous Multi-Core Platforms

Koen Bertels, Roel Meeuws, S. Arash Ostadzadeh

How Parameterizable Run-time FPGA Reconfiguration can Benefit Adaptive Embedded Systems

Dirk Stroobandt, Karel Bruneel

SESSION: REGULAR PAPERS

A Transparent and Adaptable Multiple-ISA Embedded System

Mateus Beck Rutzig, Jair Fajardo Jr, Luigi Carro, Antonio Carlos Schneider Beck

SESSION: INVITED SESSION - HOW TO EFFECTIVELY PROGRAM RECONFIGURABLE

MULTI-CORE EMBEDDED SYSTEMS?

INVITED TALKS

How to Effectively Program Reconfigurable Multi-Core Embedded Systems?

Pedro Pedro Diniz

Heterogeneous Multicore Computing Challenges And Opportunities

Koen Bertels, Vlad-Mihai Sima, Georgi Kuzmanov

Runtime Resource Management Techniques for Many-core Architectures The 2PARMA Approach

Alexandros Bartzas, Patrick Bellasi, Iraklis Anagnostopoulos, Cristina Silvano, William Fornaciari, Dimitrios Soudris, Diego Melpignano, Chantal Ykman-Couvreur

A New Approach to Control and Guide the Mapping of Computations to FPGAs

Joao Cardoso, Razvan Nane, Pedro Diniz, Zlatko Petrov, Kamil Kratky, Koen Bertels, Michael Huebner, Fernando Goncalves, Jose Coutinho, George Constantinides, Bryan Olivier, Wayne Luk, Juergen Becker, Georgi Kuzmanov

SESSION: REGULAR PAPERS

A Heterogeneous Reconfigurable System-on-Chip: MORPHEUS

Florian Thoma, Matthias Kuhnle, Arnaud Grasset, Paul Brelet, Philippe Millet, Philippe Bonnot, Fabio Campi, Nikolaos S. Voros, Wolfram Putzke-Roeming, Axel Schneider, Michael Huebner, Klaus D. Muller-Glaser, Jurgen Becker

SESSION: REGULAR SESSION - ADAPTIVE AND RECONFIGURABLE HARDWARE

Design Flows and Run Time Systems for Heterogeneous Multiprocessor Systems on Programmable Chips (MPSoPCs)

David Andrews

Can Run-time Reconfigurable Hardware be more Accessible?

Jim Torresen, Dirk Koch

SAHA: A Self-Adaptive Hardware-Software System Architecture for Ubiquitous Computing Applications

Pao-Ann Hsiung, Chun-Hsian Huang

SESSION: REGULAR PAPERS

Evaluating Expression Trees in Hardware

Lars Middendorf, Christophe Bobda

Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors

Yosuke Ohbayashi, Hasitha Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

Placement and Routing Algorithm for Pipeline Architecture

Mayuko Koezuka, Akira Kuroda, Kenji Funaoka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano

Accelerating Real-time processing of the ATST Adaptive Optics System using Coarse-grained Parallel Hardware Architectures

Vivek Venugopal, Kit Richards, Sam Barden, Thomas Rimmele, Brian Gregory, Luke Johnson

A New Hardware/Software Partitioning Methodology Combining Search Space Smoothing and Discrete Particle Swarm Optimization

Yu Chen, Pranav Vaidya, Jaehwan Lee, Chandima Nadungodage, Yuni Xia, Ren-fa Li, Qiang Wu

Dynamic Reconfiguration on a Dynamically Reconfigurable Vision-chip Architecture

Amarjargal Gundjalam, Minoru Watanabe

A Scalable FPGA Vehicle Monitoring and Classification Architecture

Francis Bowen, Jaehwan Lee, Eliza Du

SESSION: SHORT PAPERS

The Tools Have Arrived: Two-Command Compilation and Execution of Scalable, Multi-FPGA Applications

Brian Holland

Statistical Data Generation System for Scientific Applications

Andrea Abba, Francesco Caponio, Paolo Baruzzi, Angelo Geraci, Giancarlo Ripamonti

An FPGA Based on Synchronous/Asynchronous Hybrid Architecture with Area-Efficient FIFO Interfaces

Masanori Hariyama, Yoshiya Komatsu, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama

SESSION: POSTERS

Synthesis of Simulink based Models for Parallel Architectures including FPGAs and Multi-core Processors for an Infrared Scene Generator System

Rhonda Gaede, Chris Smeal, Jeff Kulick

SESSION: LATE PAPERS

Cybersecurity: From Engineering to Science

Carl Landwehr

Rapid Implementation of Floating-point Computations Using Phase-coherent Dynamically

Configurable Pipelines

David Rutishauser, Robert Shuler

NAC: A Lightweight Intermediate Representation for ASIP Compilers

Nikolaos Kavvadias, Konstantinos Masselos

Automatic Tailoring of Configurable Vector Processors for Scientific Computations

David Rutishauser, Mark Jones

Optimizing the Costs of Communication Infrastructure in Message-Based Multicore

Lars Middendorf, Christian Haubelt, Christophe Bobda

A Reconfigurable Computing Multiple Processor Framework with Hybrid Pipeline Scheduling

Darcy Cook, Ken Ferens, Bob McLeod