CDES'11
The 2011 International Conference on Computer Design
ISBN #: 1-60132-173-2 EDITORS: Hamid R. Arabnia and Ashu M. G. Solo
SESSION: PERFORMANCE ISSUES AND ENHANCEMENT METHODS + POWER ANALYSIS
Virtual Page Placement Guided by DRAM Locality and Latency
Brian Davis, Daniel Bassett, Aabhas Agarwal
Standby Power Reduction Techniques for Asynchronous Circuits with Indeterminate Standby States
Liang Zhou, Scott Smith
The Impact of Dust on On-chip Temperature And Performance of Microprocessors
Hyung Beom Jang, Cheol Hong Kim, Sung Woo Chung
Performance Improvement by N-Chance Clustered Caching in NoC based Chip Multi-Processors
Rakesh Yarlagadda, Sanmukh R Kuppannagari, Hemangee K. Kapoor
SESSION: ALGORITHMS, LOGIC, CIRCUIT/HARDWARE DESIGN, AND TOOLS
Synchronization of Different Chaotic Systems and Electronic Circuit Analysis
J. H. Park, T. H. Lee, D. H. Ji, H. Y. Jung, S. M. Lee
Improved Cost Reversible Multiplier Design
Mihail Cutitaru, Lee A. Belfore, II
Advancement On Optical Transition Logic
Parteek Sharma, Gagandeep Sharma, Richa Sharma
Designing a Secure 32-bit ALU using (63, 36) BCH code
Vahid Khorasani, Mohammad Mortazavi, Bijan Vousoghi Vahdat
Dealing with the 'Itanium Effect'
Steve Richfield
Analysis of 32-bit Fault Tolerant ALU Methods
Vahid Khorasani, Bijan Vousoghi Vahdat, Mohammad Mortazavi
SESSION: HPC AND DESIGN ISSUES + FPGA + GPU + NOC + EMBEDDED SYSTEMS
High-Performance and Area-Efficient Hardware Design for Radix-2k Montgomery Multipliers
Liang Zhou, Miaoqing Huang, Scott Smith
Sensitivity Analysis on Hardware Resources in SMT Processors
Naveen Davanam, Ho Young Kim, Byeong Kil Lee, Eugene John
Hardware Design and Implementation of Digital Pulse Processor using FPGA
Sanghoon Yang, Cheoljin Choi, Sook Yoon, Dong Sun Park
Ken Hawick, Daniel Playne, Mitchell Johnson
Clustered Caching for Improving Performance and Energy Requirements in NoC Based Multiprocessors
Hemangee K. Kapoor, Lopamudra Chatterjee, Rakesh Yarlagadda
SESSION: GENERAL TOPICS AND DISCUSSIONS
Evaluation of Enhanced Replacement Scheme (ERS) on Simplescalar Simulation Tool
Manoj Kumar, Anand Mohan, Gaurav Gupta
Computerized Sale and Distribution System and Its Economical Analysis
Maryam Hamedanian
Raj Shankar
SESSION: ASYNCHRONOUS DESIGN + MULTI-CORE PROCESSORS + FPGA + HPC +
CIRCUIT DESIGN
Robust Asynchronous Carry Lookahead Adders
P. Balasubramanian, D. A. Edwards, H. R. Arabnia
Reducing Thermal Hotspots in Multi-Core Processors using Core Migration Scheduling
Savithra Eratne, Claudia Romo, Eugene John, Wei-Ming Lin
Simple QPSK Modulator Implemented in Virtex 6 FPGA Board for Satellite Ground Station
Asraf Mohamed Moubark, Mohd Alauddin Mohd Ali, Sawal Ali, Hilmi Sanusi, Nasharuddin Zainal
Improved Floating-Point Matrix Multiplier
Wei-Ting Weng, Dyi-Rong Duh
High Speed Performance and Yield Optimization Technique for Analog Integrated Circuits
Sawal Ali, Md. Shabiul Islam, Siti A. Ahmad
Leakage - Delay Tradeoff in Wide-Bit Nanoscale CMOS Adders
Claudia Romo, Savithra Eratne, Eugene John, Byeong Lee